Thursday, October 10, 2013
1 Cent RFID- The Future
1 Cent RFID- The Future
“Manufacturing Cost Simulations for Low Cost RFID systems” did a cost analysis and simulated manufacturing and assembly processes to examine the feasibility of the 5¢ tag. They did so assuming large volumes are being manufactured – achieving which is, of course, another challenge entirely. They experimented with variations in process, throughput and component variables to estimate what will be required to approach the 5¢ goal. As part of this experiment, they examined both the semiconductor manufacturing and the assembly of RFID tags. Their approach consists of two steps: benchmarking the processes employed and the equipment used, and cost model simulation using this benchmark data. I won’t dive into the technology here.
The white paper I found here, incidentally by a CMU alumnus , who went on to do his PhD at UC Berkeley, Sanjay Sharma developed a model for costing RFID tags which is similar to the approach used in the semiconductor industry. His team speculated that it is indeed possible to achieve a 5¢/tag cost number at a sufficiently high volume of tags using even existing technology. The volume required to reach this cost metric is well within the reach of current fab capacities. Process innovations and improvements that drive down antenna costs will also significantly impact the cost per tag. These innovations are connected to each other. For example, lower powered dies will reduce the conductivity required of the antenna, enabling even lower cost printed antennas. In other words, aggressive thinking and innovations in RFID tag manufacturing will reveal numerous synergies which can play off each other in the coming years, providing additional cost reductions.
Further innovations may allow us to push the costs lower –a 20 mask, 2 metal process can possibly allow them to push the silicon cost below 1C. For the assembly portion, assuming antenna costs can be pushed as low as 1¢, it is possible to assemble the tag for 3.3¢ at very high volumes using a traditional assembly process and 2.08¢ using an innovative flip-chip manufacturing process. If the number of wafer starts is increased by a factor of 10 to a total of 3 million wafer starts per year, the silicon costs can be brought to under 1¢ as well.
Unfortunately, the industry today seems trapped in “catalog mode” where engineers are forced to pick inappropriate machines from catalogs rather than inventing solutions to critical problems. Volumes, roadmaps and, most importantly, orders will surely unleash a new cycle of much-needed innovation.
My question is, how big is big enough? What is the minimum volume of wafers needed to optimally minimize the total cost of a single wafer?